Low Power MSIC Signatures for Effective BIST Design

Multiple Single Input Change Vectors for Built-In Self Test (MSIC-BIST)

A Modified Clock Scheme for a Low Power BIST Test Pattern Generator

In this paper, we present a new low power BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique. The fault coverage and the test time are roug...

Pattern Mapping Method for Low Power BIST Based on Transition Freezing Method

Proposed in this paper is a low power BIST architecture using the pattern mapping method based on the transition freezing method. The transition freezing method generates frozen patterns dynamically according to the transition tendency of an LFSR. This leads to an average power reduction of 60%. However, the patterns have limitations of 100% fault coverage due to random resistant faults. Theref...

Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST

of-the-art chip designs to improve test quality and reduce the cost of test development and application. Despite such benefits, designers have not adopted BIST as the primary test methodology. Fault diagnosis in a BIST environment is problematic because only limited information is available in a compact signature like that produced with BIST. Previous techniques have focused on extracting infor...

Low Power BIST for Wallace Tree-Based Fast Multipliers

The low power as a feature of a BIST scheme is a significant target due to quality as well as cost related issues. In this paper we examine the testability of multipliers based on Booth encoding and Wallace tree summation of the partial products and we present a methodology for deriving a low power Built In Self Test (BIST) scheme for them. We propose several design rules for designing the Wall...